In integrated circuit (IC) manufacturing, a semiconductor wafer typically contains a plurality of test line structures in the scribe line area between adjacent wafer dies. Each test line structure includes one or more test devices, which are devices similar to those that are normally used to form the integrated circuit products in the wafer die area. By studying the test line structures, it is possible to monitor, improve, and refine a semiconductor manufacturing process.
With the continuing scale-down of IC device feature sizes, integrated circuit device density and functional complexity are continuously increasing. This trend imposes new challenges on the existing test line structures and test methodologies. One of these challenges is to test such parameters as sheet resistance (Rs), critical dimension (CD) and thickness of Cu trench structures.